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ispMACH 4000ZE Family
1.8V In-System Programmable Ultra Low Power PLDs
August 2008 Data Sheet DS1022
(R)
Features
High Performance
* fMAX = 260MHz maximum operating frequency * tPD = 4.4ns propagation delay * Up to four global clock pins with programmable clock polarity control * Up to 80 PTs per output
Broad Device Offering
* 32 to 256 macrocells * Multiple temperature range support - Commercial: 0 to 90C junction (Tj) - Industrial: -40 to 105C junction (Tj) * Space-saving packages
Easy System Integration
* Operation with 3.3V, 2.5V, 1.8V or 1.5V LVCMOS I/O * 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI interfaces * Hot-socketing support * Open-drain output option * Programmable output slew rate * 3.3V PCI compatible * I/O pins with fast setup path * Input hysteresis* * 1.8V core power supply * IEEE 1149.1 boundary scan testable * IEEE 1532 ISC compliant * 1.8V In-System Programmable (ISPTM) using Boundary Scan Test Access Port (TAP) * Pb-free package options (only) * On-chip user oscillator and timer*
Ease of Design
* Flexible CPLD macrocells with individual clock, reset, preset and clock enable controls * Up to four global OE controls * Individual local OE control per I/O pin * Excellent First-Time-FitTM and refit * Wide input gating (36 input logic blocks) for fast counters, state machines and address decoders
Ultra Low Power
* * * * Standby current as low as 10A typical 1.8V core; low dynamic power Operational down to 1.6V VCC Superior solution for power sensitive consumer applications * Per pin pull-up, pull-down or bus keeper control* * Power Guard with multiple enable signals*
*New enhanced features over original ispMACH 4000Z
Table 1. ispMACH 4000ZE Family Selection Guide
ispMACH 4032ZE Macrocells tPD (ns) tS (ns) tCO (ns) fMAX (MHz) Supply Voltages (V) Packages1 (I/O + Dedicated Inputs) 48-Pin TQFP (7 x 7mm) 64-Ball csBGA (5 x 5mm) 100-Pin TQFP (14 x 14mm) 144-Pin TQFP (20 x 20mm) 144-Ball csBGA (7 x 7mm)
1. Pb-free only.
ispMACH 4064ZE 64 4.7 2.5 3.2 241 1.8V 32+4 48+4 64+10 64+10
ispMACH 4128ZE 128 5.8 2.9 3.8 200 1.8V
ispMACH 4256ZE 256 5.8 2.9 3.8 200 1.8V
32 4.4 2.2 3.0 260 1.8V 32+4 32+4
64+10 96+4 96+4
64+10 96+14 108+4
(c) 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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DS1022_01.2
Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
Introduction
The high performance ispMACH 4000ZE family from Lattice offers an ultra low power CPLD solution. The new family is based on Lattice's industry-leading ispMACH 4000 architecture. Retaining the best of the previous generation, the ispMACH 4000ZE architecture focuses on significant innovations to combine high performance with low power in a flexible CPLD family. For example, the family's new Power Guard feature minimizes dynamic power consumption by preventing internal logic toggling due to unnecessary I/O pin activity. The ispMACH 4000ZE combines high speed and low power with the flexibility needed for ease of design. With its robust Global Routing Pool and Output Routing Pool, this family delivers excellent First-Time-Fit, timing predictability, routing, pin-out retention and density migration. The ispMACH 4000ZE family offers densities ranging from 32 to 256 macrocells. There are multiple density-I/O combinations in Thin Quad Flat Pack (TQFP) and Chip Scale BGA (csBGA) packages ranging from 32 to 176 pins/ balls. Table 1 shows the macrocell, package and I/O options, along with other key parameters. A user programmable internal oscillator and a timer are included in the device for tasks like LED control, keyboard scanner and similar housekeeping type state machines. This feature can be optionally disabled to save power. The ispMACH 4000ZE family has enhanced system integration capabilities. It supports a 1.8V supply voltage and 3.3V, 2.5V, 1.8V and 1.5V interface voltages. Additionally, inputs can be safely driven up to 5.5V when an I/O bank is configured for 3.3V operation, making this family 5V tolerant. The ispMACH 4000ZE also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. Pull-up, pull-down and bus-keeper features are controllable on a "per-pin" basis. The ispMACH 4000ZE family members are 1.8V in-system programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1 boundary scan testing capability also allows product testing on automated test equipment. The 1532 interface signals TCK, TMS, TDI and TDO are referenced to VCC (logic core).
Overview
The ispMACH 4000ZE devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) interconnected by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O Blocks (IOBs), which contain multiple I/O cells. This architecture is shown in Figure 1. Figure 1. Functional Block Diagram
CLK0/I CLK1/I CLK2/I CLK3/I VCCO0 GND VCCO1 GND
I/O Block 16 ORP
GOE0 GOE1
VCC GND
OSC
I/O Block ORP 16
Global Routing Pool
Generic Logic Block
16 36
16 36
Generic Logic Block
I/O Bank 0
TCK TMS TDI TDO
I/O Block ORP 16
Generic Logic Block
16 36
16 36
Generic Logic Block
I/O Block 16 ORP
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I/O Bank 1
Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
The I/Os in the ispMACH 4000ZE are split into two banks. Each bank has a separate I/O power supply. Inputs can support a variety of standards independent of the chip or bank power supply. Outputs support the standards compatible with the power supply provided to the bank. Support for a variety of standards helps designers implement designs in mixed voltage environments. In addition, 5V tolerant inputs are specified within an I/O bank that is connected to a VCCO of 3.0V to 3.6V for LVCMOS 3.3, LVTTL and PCI interfaces.
Architecture
There are a total of two GLBs in the ispMACH 4032ZE, increasing to 16 GLBs in the ispMACH 4256ZE. Each GLB has 36 inputs. All GLB inputs come from the GRP and all outputs from the GLB are brought back into the GRP to be connected to the inputs of any other GLB on the device. Even if feedback signals return to the same GLB, they still must go through the GRP. This mechanism ensures that GLBs communicate with each other with consistent and predictable delays. The outputs from the GLB are also sent to the ORP. The ORP then sends them to the associated I/O cells in the I/O block.
Generic Logic Block
The ispMACH 4000ZE GLB consists of a programmable AND array, logic allocator, 16 macrocells and a GLB clock generator. Macrocells are decoupled from the product terms through the logic allocator and the I/O pins are decoupled from macrocells through the ORP. Figure 2 illustrates the GLB. Figure 2. Generic Logic Block
CLK0 CLK1 CLK2 CLK3
To GRP
Clock Generator 1+OE
16 MC Feedback Signals
1+OE
1+OE 1+OE 1+OE 1+OE 1+OE 1+OE To Product Term Output Enable Sharing. Also, To Input Enable of Power Guard on I/Os in the block.
Logic Allocator
AND Array 36 Inputs, 83 Product Terms
16 Macrocells
36 Inputs from GRP
AND Array
The programmable AND Array consists of 36 inputs and 83 output product terms. The 36 inputs from the GRP are used to form 72 lines in the AND Array (true and complement of the inputs). Each line in the array can be connected to any of the 83 output product terms via a wired-AND. Each of the 80 logic product terms feed the logic allocator with the remaining three control product terms feeding the Shared PT Clock, Shared PT Initialization and Shared PT OE. The Shared PT Clock and Shared PT Initialization signals can optionally be inverted before being fed to the macrocells. Every set of five product terms from the 80 logic product terms forms a product term cluster starting with PT0. There is one product term cluster for every macrocell in the GLB. Figure 3 is a graphical representation of the AND Array. 3
To ORP
Lattice Semiconductor
Figure 3. AND Array
In[0] In[34] In[35]
ispMACH 4000ZE Family Data Sheet
PT0 PT1 PT2 PT3 PT4
Cluster 0
PT75 PT76 PT77 Cluster 15 PT78 PT79 PT80 Shared PT Clock PT81 Shared PT Initialization PT82 Shared PTOE/BIE Note: Indicates programmable fuse.
Enhanced Logic Allocator
Within the logic allocator, product terms are allocated to macrocells in product term clusters. Each product term cluster is associated with a macrocell. The cluster size for the ispMACH 4000ZE family is 4+1 (total 5) product terms. The software automatically considers the availability and distribution of product term clusters as it fits the functions within a GLB. The logic allocator is designed to provide two speed paths: 20-PT Speed Locking path and an up to 80-PT path. The availability of these two paths lets designers trade timing variability for increased performance. The enhanced Logic Allocator of the ispMACH 4000ZE family consists of the following blocks: * Product Term Allocator * Cluster Allocator * Wide Steering Logic Figure 4 shows a macrocell slice of the Logic Allocator. There are 16 such slices in the GLB. Figure 4. Macrocell Slice
to to n-1 n-2 from from n-1 n-4
From n-4 n 5-PT
1-80 PTs To XOR (MC)
Cluster
to n+1 Individual Product Term Allocator
from from n+2 n+1 Cluster Allocator
To n+4 SuperWIDETM Steering Logic
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Lattice Semiconductor Product Term Allocator
ispMACH 4000ZE Family Data Sheet
The product term allocator assigns product terms from a cluster to either logic or control applications as required by the design being implemented. Product terms that are used as logic are steered into a 5-input OR gate associated with the cluster. Product terms that used for control are steered either to the macrocell or I/O cell associated with the cluster. Table 2 shows the available functions for each of the five product terms in the cluster. Table 2. Individual PT Steering
Product Term PTn PTn+1 PTn+2 PTn+3 PTn+4 Logic Logic PT Logic PT Logic PT Logic PT Logic PT Single PT for XOR/OR Individual Clock (PT Clock) Individual Initialization or Individual Clock Enable (PT Initialization/CE) Individual Initialization (PT Initialization) Individual OE (PTOE) Control
Cluster Allocator
The cluster allocator allows clusters to be steered to neighboring macrocells, thus allowing the creation of functions with more product terms. Table 3 shows which clusters can be steered to which macrocells. Used in this manner, the cluster allocator can be used to form functions of up to 20 product terms. Additionally, the cluster allocator accepts inputs from the wide steering logic. Using these inputs, functions up to 80 product terms can be created. Table 3. Available Clusters for Each Macrocell
Macrocell M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 -- C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 Available Clusters C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 -- C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 -- --
Wide Steering Logic
The wide steering logic allows the output of the cluster allocator n to be connected to the input of the cluster allocator n+4. Thus, cluster chains can be formed with up to 80 product terms, supporting wide product term functions and allowing performance to be increased through a single GLB implementation. Table 4 shows the product term chains.
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Lattice Semiconductor
Table 4. Product Term Expansion Capability
Expansion Chains Chain-0 Chain-1 Chain-2 Chain-3
ispMACH 4000ZE Family Data Sheet
Macrocells Associated with Expansion Chain (with Wrap Around) M0 M4 M8 M12 M0 M1 M5 M9 M13 M1 M2 M6 M10 M14 M2 M3 M7 M11 M15 M3
Max PT/ Macrocell 75 80 75 70
Every time the super cluster allocator is used, there is an incremental delay of tEXP . When the super cluster allocator is used, all destinations other than the one being steered to, are given the value of ground (i.e., if the super cluster is steered to M (n+4), then M (n) is ground).
Macrocell
The 16 macrocells in the GLB are driven by the 16 outputs from the logic allocator. Each macrocell contains a programmable XOR gate, a programmable register/latch, along with routing for the logic and control functions. Figure 5 shows a graphical representation of the macrocell. The macrocells feed the ORP and GRP. A direct input from the I/O cell allows designers to use the macrocell to construct high-speed input registers. A programmable delay in this path allows designers to choose between the fastest possible set-up time and zero hold time. Figure 5. Macrocell
Power-up Initialization
Shared PT Initialization PT Initialization (optional) PT Initialization/CE (optional) Delay From I/O Cell
From Logic Allocator
R D/T/L
P Q
To ORP To GRP
CE
Single PT
Block CLK0 Block CLK1 Block CLK2 Block CLK3 PT Clock (optional) Shared PT Clock
Enhanced Clock Multiplexer
The clock input to the flip-flop can select any of the four block clocks along with the shared PT clock, and true and complement forms of the optional individual term clock. An 8:1 multiplexer structure is used to select the clock. The eight sources for the clock multiplexer are as follows: * Block CLK0 * Block CLK1
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Lattice Semiconductor
* * * * * * Block CLK2 Block CLK3 PT Clock PT Clock Inverted Shared PT Clock Ground
ispMACH 4000ZE Family Data Sheet
Clock Enable Multiplexer
Each macrocell has a 4:1 clock enable multiplexer. This allows the clock enable signal to be selected from the following four sources: * PT Initialization/CE * PT Initialization/CE Inverted * Shared PT Clock * Logic High
Initialization Control
The ispMACH 4000ZE family architecture accommodates both block-level and macrocell-level set and reset capability. There is one block-level initialization term that is distributed to all macrocell registers in a GLB. At the macrocell level, two product terms can be "stolen" from the cluster associated with a macrocell to be used for set/reset functionality. A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged, providing flexibility. Note that the reset/preset swapping selection feature affects power-up reset as well. All flip-flops power up to a known state for predictable system initialization. If a macrocell is configured to SET on a signal from the block-level initialization, then that macrocell will be SET during device power-up. If a macrocell is configured to RESET on a signal from the block-level initialization or is not configured for set/reset, then that macrocell will RESET on powerup. To guarantee initialization values, the VCC rise must be monotonic, and the clock must be inactive until the reset delay time has elapsed.
GLB Clock Generator
Each ispMACH 4000ZE device has up to four clock pins that are also routed to the GRP to be used as inputs. These pins drive a clock generator in each GLB, as shown in Figure 6. The clock generator provides four clock signals that can be used anywhere in the GLB. These four GLB clock signals can consist of a number of combinations of the true and complement edges of the global clock signals. Figure 6. GLB Clock Generator
CLK0 Block CLK0
CLK1
Block CLK1
CLK2 Block CLK2
CLK3
Block CLK3
7
Lattice Semiconductor Output Routing Pool (ORP)
ispMACH 4000ZE Family Data Sheet
The Output Routing Pool allows macrocell outputs to be connected to any of several I/O cells within an I/O block. This provides greater flexibility in determining the pinout and allows design changes to occur without affecting the pinout. The output routing pool also provides a parallel capability for routing macrocell-level OE product terms. This allows the OE product term to follow the macrocell output as it is switched between I/O cells. The enhanced ORP of the ispMACH 4000ZE family consists of the following elements: * Output Routing Multiplexers * OE Routing Multiplexers Figure 7 shows the structure of the ORP from the I/O cell perspective. This is referred to as an ORP slice. Each ORP has as many ORP slices as there are I/O cells in the corresponding I/O block. Figure 7. ORP Slice
OE Routing Multiplexer From PTOE To I/O Cell OE
Output Routing Multiplexer From Macrocell To I/O Cell
Output Routing Multiplexers
The details of connections between the macrocells and the I/O cells vary across devices and within a device dependent on the maximum number of I/Os available. Tables 5-7 provide the connection details. Table 5. GLB/MC/ORP Combinations for ispMACH 4256ZE
GLB/MC [GLB] [MC 0] [GLB] [MC 1] [GLB] [MC 2] [GLB] [MC 3] [GLB] [MC 4] [GLB] [MC 5] [GLB] [MC 6] [GLB] [MC 7] M0, M1, M2, M3, M4, M5, M6, M7 M2, M3, M4, M5, M6, M7, M8, M9 M4, M5, M6, M7, M8, M9, M10, M11 M6, M7, M8, M9, M10, M11, M12, M13 M8, M9, M10, M11, M12, M13, M14, M15 M10, M11, M12, M13, M14, M15, M0, M1 M12, M13, M14, M15, M0, M1, M2, M3 M14, M15, M0, M1, M2, M3, M4, M5 ORP Mux Input Macrocells
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Lattice Semiconductor
Table 6. GLB/MC/ORP Combinations for ispMACH 4128ZE
GLB/MC [GLB] [MC 0] [GLB] [MC 1] [GLB] [MC 2] [GLB] [MC 3] [GLB] [MC 4] [GLB] [MC 5] [GLB] [MC 6] [GLB] [MC 7] [GLB] [MC 8] [GLB] [MC 9] [GLB] [MC 10] [GLB] [MC 11] M0, M1, M2, M3, M4, M5, M6, M7 M1, M2, M3, M4, M5, M6, M7, M8 M2, M3, M4, M5, M6, M7, M8, M9 M4, M5, M6, M7, M8, M9, M10, M11 M5, M6, M7, M8, M9, M10, M11, M12 M6, M7, M8, M9, M10, M11, M12, M13 M8, M9, M10, M11, M12, M13, M14, M15 M9, M10, M11, M12, M13, M14, M15, M0 M10, M11, M12, M13, M14, M15, M0, M1 M12, M13, M14, M15, M0, M1, M2, M3 M13, M14, M15, M0, M1, M2, M3, M4 M14, M15, M0, M1, M2, M3, M4, M5
ispMACH 4000ZE Family Data Sheet
ORP Mux Input Macrocells
Table 7. GLB/MC/ORP Combinations for ispMACH 4032ZE and 4064ZE
GLB/MC [GLB] [MC 0] [GLB] [MC 1] [GLB] [MC 2] [GLB] [MC 3] [GLB] [MC 4] [GLB] [MC 5] [GLB] [MC 6] [GLB] [MC 7] [GLB] [MC 8] [GLB] [MC 9] [GLB] [MC 10] [GLB] [MC 11] [GLB] [MC 12] [GLB] [MC 13] [GLB] [MC 14] [GLB] [MC 15] M0, M1, M2, M3, M4, M5, M6, M7 M1, M2, M3, M4, M5, M6, M7, M8 M2, M3, M4, M5, M6, M7, M8, M9 M3, M4, M5, M6, M7, M8, M9, M10 M4, M5, M6, M7, M8, M9, M10, M11 M5, M6, M7, M8, M9, M10, M11, M12 M6, M7, M8, M9, M10, M11, M12, M13 M7, M8, M9, M10, M11, M12, M13, M14 M8, M9, M10, M11, M12, M13, M14, M15 M9, M10, M11, M12, M13, M14, M15, M0 M10, M11, M12, M13, M14, M15, M0, M1 M11, M12, M13, M14, M15, M0, M1, M2 M12, M13, M14, M15, M0, M1, M2, M3 M13, M14, M15, M0, M1, M2, M3, M4 M14, M15, M0, M1, M2, M3, M4, M5 M15, M0, M1, M2, M3, M4, M5, M6 ORP Mux Input Macrocells
Output Enable Routing Multiplexers
The OE Routing Pool provides the corresponding local output enable (OE) product term to the I/O cell.
I/O Cell
The I/O cell contains the following programmable elements: output buffer, input buffer, OE multiplexer, Power Guard and bus maintenance circuitry. Figure 8 details the I/O cell.
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Lattice Semiconductor
Figure 8. I/O Cell
GOE 0 GOE 1 GOE 2 GOE 3
ispMACH 4000ZE Family Data Sheet
I/O Bus Maintenance From ORP VCC VCCO VCCO
From ORP Power Guard
0
To Macrocell To GRP
1
Power Guard Disable Fuse (PGDF) Block Input Enable (BIE) (From Block PT)
Each output supports a variety of output standards dependent on the VCCO supplied to its I/O bank. Outputs can also be configured for open drain operation. Each input can be programmed to support a variety of standards, independent of the VCCO supplied to its I/O bank. The I/O standards supported are: * LVTTL * LVCMOS 3.3 * LVCMOS 2.5 * LVCMOS 1.8 * LVCMOS 1.5 * 3.3V PCI Compatible
All of the I/Os and dedicated inputs have the capability to provide a bus-keeper latch, pull-up resistor or pull-down resistor selectable on a "per-pin" basis. A fourth option is to provide none of these. The default in both hardware and software is such that when the device is erased or if the user does not specify, the input structure is configured to be a Pull-down Resistor. Each ispMACH 4000ZE device I/O has an individually programmable output slew rate control bit. Each output can be individually configured for fast slew or slow slew. The typical edge rate difference between fast and slow slew setting is 20%. For high-speed designs with long, unterminated traces, the slow-slew rate will introduce fewer reflections, less noise and keep ground bounce to a minimum. For designs with short traces or well terminated lines, the fast slew rate can be used to achieve the highest speed. The ispMACH 4000ZE family has an always on, 200mV typical hysteresis for each input operational at 3.3V and 2.5V. This provides improved noise immunity for slow transitioning signals.
Power Guard
Power Guard allows easier achievement of standby current in the system. As shown in Figure 9, this feature consists of an enabling multiplexer between an I/O pin and input buffer, and its associated circuitry inside the device. If the enable signal (E) is held low, all inputs (D) can be optionally isolated (guarded), such that, if any of these were toggled, it would not cause any toggle on internal pins (Q), thus, a toggling I/O pin will not cause any internal dynamic power consumption.
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Lattice Semiconductor
Figure 9. Power Guard
Power Guard
ispMACH 4000ZE Family Data Sheet
D
0 1 E
Q
All the I/O pins in a block share a common Power Guard Enable signal. For a block of I/Os, this signal is called a Block Input Enable (BIE) signal. BIE can be internally generated using MC logic, or could come from external sources using one of the user I/O or input pins. Any I/O pin in the block can be programmed to ignore the BIE signal. Thus, the feature can be enabled or disabled on a pin-by-pin basis. Figure 10 shows Power Guard and BIE across multiple I/Os in a block that has eight I/Os. Figure 10. Power Guard and BIE in a Block with 8 I/Os
Power Guard
0
To Macrocell To GRP
1
I/O 0
Power Guard
0
To Macrocell To GRP
1
I/O 1
Block Input Enable (BIE) From Block PT. The Block PT is part of the block AND Array, and can be driven by signals from the GRP. Power Guard
0
To Macrocell To GRP
1
I/O 7
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
The number of BIE inputs, thus the number of Power Guard "Blocks" that can exist in a device, depends on the device size. Table 8 shows the number of BIE signals available in the ispMACH 4000ZE family. The number of I/Os available in each block is shown in the Ordering Information section of this data sheet. Table 8. Number of BIE Signals Available in ispMACH 4000ZE Devices
Device ispMACH 4032ZE ispMACH 4064ZE ispMACH 4128ZE ispMACH 4256ZE Number of Logic Blocks, Power Guard Blocks and BIE Signals Two (Blocks: A and B) Four (Blocks: A, B, C and D) Eight (Blocks: A, B, C, ..., H) Sixteen (Blocks: A, B, C, ..., P)
Power Guard for Dedicated Inputs
Power Guard can optionally be applied to the dedicated inputs. The dedicated inputs and clocks are controlled by the BIE of the logic blocks shown in Tables 9 and 10. Table 9. Dedicated Clock Inputs to BIE Association
CLK/I CLK0 / I CLK1 / I CLK2 / I CLK3 / I 32 MC Block A A B B 64MC Block A B C D 128MC Block A D E H 256MC Block A H I P
Table 10. Dedicated Inputs to BIE Association
Dedicated Input 0 1 2 3 4 5 6 7 8 9 4064ZE Block A B B C D D -- -- -- -- 4128ZE Block B C D F G H -- -- -- -- 4256ZE Block D E G G J L M O O B
For more information on the Power Guard function refer to TN1174, Advanced Features of the ispMACH 4000ZE.
Global OE (GOE) and Block Input Enable (BIE) Generation
Most ispMACH 4000ZE family devices have a 4-bit wide Global OE (GOE) Bus (Figure 11), except the ispMACH 4032 device that has a 2-bit wide Global OE Bus (Figure 12). This bus is derived from a 4-bit internal global OE (GOE) PT bus and two dual purpose I/O or GOE pins. Each signal that drives the bus can optionally be inverted. Each GLB has a block-level OE PT that connects to all bits of the Global OE PT bus with four fuses. Hence, for a 256-macrocell device (with 16 blocks), each line of the bus is driven from 16 OE product terms. Figures 9 and 10 show a graphical representation of the global OE generation. The block-level OE PT of each GLB is also tied to Block Input Enable (BIE) of that block. Hence, for a 256-macrocell device (with 16 blocks), each block's BIE signal is driven by block-level OE PT from each block. 12
Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
Figure 11. Global OE Generation for All Devices Except ispMACH 4032ZE
Internal Global OE PT Bus (4 lines) Global OE 4-Bit Global OE Bus
Shared PTOE (Block 0) Shared PTOE (Block n)
BIE0 BIEn
Global Fuses
Fuse connection Hard wired
GOE (0:3) to I/O cells
Figure 12. Global OE Generation for ispMACH 4032ZE
Internal Global OE PT Bus (2 lines) 4-Bit Global OE Bus
Global OE
Shared PTOE (Block 0) Shared PTOE (Block 1)
BIE0 BIE1
Global Fuses
Fuse connection Hard wired
GOE (3:0) to I/O cells
On-Chip Oscillator and Timer
An internal oscillator is provided for use in miscellaneous housekeeping functions such as watchdog heartbeats, digital de-glitch circuits and control state machines. The oscillator is disabled by default to save power. Figure 13 shows the block diagram of the oscillator and timer block.
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Lattice Semiconductor
Figure 13. On-Chip Oscillator and Timer
DYNOSCDIS OSCTIMER TIMERRES
ispMACH 4000ZE Family Data Sheet
OSCOUT TIMEROUT
Table 11. On-Chip Oscillator and Timer Signal Names
Signal Name OSCOUT TIMEROUT TIMERRES DYNOSCDIS Input or Output Output Output Input Input Optional / Required Optional Optional Optional Optional Description Oscillator Output (Nominal Frequency: 5MHz) Oscillator Frequency Divided by an integer TIMER_DIV (Default 128) Reset the Timer Disables the Oscillator, resets the Timer and saves the power.
OSCTIMER has two outputs, OSCOUT and TIMEROUT. The outputs feed into the Global Routing Pool (GRP). From GRP, these signals can drive any macrocell input, as well as any output pin (with macrocell bypass). The output OSCOUT is the direct oscillator output with a typical frequency of 5MHz, whereas, the output TIMEROUT is the oscillator output divided by an attribute TIMER_DIV. The attribute TIMER_DIV can be: 128 (7 bits), 1024 (10 bits) or 1,048,576 (20 bits). The divided output is provided for those user situations, where a very slow clock is desired. If even a slower toggling clock is desired, then the programmable macrocell resources can be used to further divide down the TIMEROUT output. Figure 14 shows the simplified relationship among OSCOUT, TIMERRES and TIMEROUT. In the diagram, the signal "R" is an internal reset signal that is used to synchronize TIMERRES to OSCOUT. This adds one extra clock cycle delay for the first timer transition after TIMERRES. Figure 14. Relationship Among OSCOUT, TIMERRES and TIMEROUT
-1 0 1 2 2n / 2 2n
OSCOUT MPW TIMERRES
R (Internal) TIMEROUT Note: n = Number of bits in the divider (7, 10 or 20) Metastability: If the signal TIMERRES is not synchronous to OSCOUT, it could make a difference of one or two clock cycles to the TIMEROUT going high the first time.
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Lattice Semiconductor Some Simple Use Scenarios
ispMACH 4000ZE Family Data Sheet
The following diagrams show a few simple examples that omit optional signals for the OSCTIMER block: A. An oscillator giving 5MHz nominal clock B. An oscillator that can be disabled with an external signal (5MHz nominal clock) C. An oscillator giving approximately 5 Hz nominal clock (TIMER_DIV = 220 (1,048,576)) D. An oscillator giving two output clocks: ~5MHz and ~5KHz (TIMER_DIV= 210 (1,024))
OSCTIME R TI ME R_DIV= N /A OSCTIME R TI ME R_DIV= N /A
OSCOUT
DYNOS CD IS
OSCOUT
(A) A simple 5MHz oscillator.
(B) An oscillator with dynamic disable.
OSCTIME R 20 TI ME R_DIV= 2
(C) A simple 5Hz oscillator.
TIMEROUT
OSCTIME R 10 TI ME R_DIV= 2
OSCOUT TIMEROUT
(D) Oscillator with two outputs (5MHz and 5KHz).
OSCTIMER Integration With CPLD Fabric
The OSCTIMER is integrated into the CPLD fabric using the Global Routing Pool (GRP). The macrocell (MC) feedback path for two macrocells is augmented with a programmable multiplexer, as shown in Figure 15. The OSCTIMER outputs (OSCOUT and TIMEROUT) can optionally drive the GRP lines, whereas the macrocell outputs can drive the optional OSCTIMER inputs TIMERRES and DYNOSCDIS. Figure 15. OSCTIMER Integration With CPLD Fabric
A Regular Macrocell To GRP Macrocell Feedback Signal
OSC Macrocell To GRP
1 0
Macrocell 15 Feedback Signal
OSCOUT DYNOSCDIS
TIMER Macrocell To GRP
1 0
Macrocell 15 Feedback Signal
TIMEROUT TIMERRES
Table 12 shows how these two MCs are designated in each of the ispMACH4000ZE device.
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Lattice Semiconductor
Table 12. OSC and TIMER MC Designation
Device ispMACH 4032ZE ispMACH 4064ZE ispMACH 4128ZE ispMACH 4256ZE Macrocell OSC MC TIMER MC OSC MC TIMER MC OSC MC TIMER MC OSC MC TIMER MC
ispMACH 4000ZE Family Data Sheet
Block Number A B A D A G C F
MC Number 15 15 15 15 15 15 15 15
Zero Power/Low Power and Power Management
The ispMACH 4000ZE family is designed with high speed low power design techniques to offer both high speed and low power. With an advanced E2 low power cell and non sense-amplifier design approach (full CMOS logic approach), the ispMACH 4000ZE family offers fast pin-to-pin speeds, while simultaneously delivering low standby power without needing any "turbo bits" or other power management schemes associated with a traditional senseamplifier approach. The zero power ispMACH 4000ZE is based on the 1.8V ispMACH 4000Z family. With innovative circuit design changes, the ispMACH 4000ZE family is able to achieve the industry's lowest static power.
IEEE 1149.1-Compliant Boundary Scan Testability
All ispMACH 4000ZE devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic notes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test node data to be captured and shifted out for verification. In addition, these devices can be linked into a board-level serial scan path for more board-level testing. The test access port operates with an LVCMOS interface that corresponds to the power supply voltage.
I/O Quick Configuration
To facilitate the most efficient board test, the physical nature of the I/O cells must be set before running any continuity tests. As these tests are fast, by nature, the overhead and time that is required for configuration of the I/Os' physical nature should be minimal so that board test time is minimized. The ispMACH 4000ZE family of devices allows this by offering the user the ability to quickly configure the physical nature of the I/O cells. This quick configuration takes milliseconds to complete, whereas it takes seconds for the entire device to be programmed. Lattice's ispVMTM System programming software can either perform the quick configuration through the PC parallel port, or can generate the ATE or test vectors necessary for a third-party test system.
IEEE 1532-Compliant In-System Programming
Programming devices in-system provides a number of significant benefits including: rapid prototyping, lower inventory levels, higher quality and the ability to make in-field modifications. All ispMACH 4000ZE devices provide InSystem Programming (ISPTM) capability through the Boundary Scan Test Access Port. This capability has been implemented in a manner that ensures that the port remains complaint to the IEEE 1149.1 standard. By using IEEE 1149.1 as the communication interface through which ISP is achieved, users get the benefit of a standard, welldefined interface. All ispMACH 4000ZE devices are also compliant with the IEEE 1532 standard. The ispMACH 4000ZE devices can be programmed across the commercial temperature and voltage range. The PC-based Lattice software facilitates in-system programming of ispMACH 4000ZE devices. The software takes the JEDEC file output produced by the design implementation software, along with information about the scan chain, and creates a set of vectors used to drive the scan chain. The software can use these vectors to drive a scan chain via the parallel port of a PC. Alternatively, the software can output files in formats understood by common auto-
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
mated test equipment. This equipment can then be used to program ispMACH 4000ZE devices during the testing of a circuit board.
User Electronic Signature
The User Electronic Signature (UES) allows the designer to include identification bits or serial numbers inside the device, stored in E2CMOS memory. The ispMACH 4000ZE device contains 32 UES bits that can be configured by the user to store unique data such as ID codes, revision numbers or inventory control codes.
Security Bit
A programmable security bit is provided on the ispMACH 4000ZE devices as a deterrent to unauthorized copying of the array configuration patterns. Once programmed, this bit defeats readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. Programming and verification are also defeated by the security bit. The bit can only be reset by erasing the entire device.
Hot Socketing
The ispMACH 4000ZE devices are well-suited for applications that require hot socketing capability. Hot socketing a device requires that the device, during power-up and down, can tolerate active signals on the I/Os and inputs without being damaged. Additionally, it requires that the effects of I/O pin loading be minimal on active signals. The ispMACH 4000ZE devices provide this capability for input voltages in the range 0V to 3.0V.
Density Migration
The ispMACH 4000ZE family has been designed to ensure that different density devices in the same package have the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration from lower density parts to higher density parts. In many cases, it is possible to shift a lower utilization design targeted for a high density device to a lower density device. However, the exact details of the final resource utilization will impact the likely success in each case.
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
Absolute Maximum Ratings1, 2, 3
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V Output Supply Voltage (VCCO) . . . . . . . . . . . . . . . -0.5 to 4.5V Input or I/O Tristate Voltage Applied4, 5 . . . . . . . . . -0.5 to 5.5V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . -65 to 150C Junction Temperature (Tj) with Power Applied . . . -55 to 150C
1. Stress above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 2. Compliance with Lattice Thermal Management document is required. 3. All voltages referenced to GND. 4. Undershoot of -2V and overshoot of (VIH (MAX) + 2V), up to a total pin voltage of 6V is permitted for a duration of <20ns. 5. Maximum of 64 I/Os per device with VIN > 3.6V is allowed.
Recommended Operating Conditions
Symbol VCC Tj Supply Voltage Junction Temperature (Commercial) Junction Temperature (Industrial) Parameter Standard Voltage Operation Extended Voltage Operation Min. 1.7 1.6 0 -40
1
Max. 1.9 1.9 90 105
Units V V C C
1. Devices operating at 1.6V can expect performance degradation up to 35%.
Erase Reprogram Specifications
Parameter Erase/Reprogram Cycle
Note: Valid over commercial temperature range.
Min. 1,000
Max. --
Units Cycles
Hot Socketing Characteristics1,2,3
Symbol IDK Parameter Input or I/O Leakage Current Condition 0 VIN 3.0V, Tj = 105C 0 VIN 3.0V, Tj = 130C Min. -- -- Typ. 30 30 Max. 150 200 Units A A
1. Insensitive to sequence of VCC or VCCO. However, assumes monotonic rise/fall rates for VCC and VCCO, provided (VIN - VCCO) 3.6V. 2. 0 < VCC < VCC (MAX), 0 < VCCO < VCCO (MAX). 3. IDK is additive to IPU, IPD or IBH. Device defaults to pull-up until fuse circuitry is active.
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
I/O Recommended Operating Conditions
VCCO (V)1 Standard LVTTL LVCMOS 3.3 Extended LVCMOS 3.3 LVCMOS 2.5 LVCMOS 1.8 LVCMOS 1.5 PCI 3.3 Min. 3.0 3.0 2.7 2.3 1.65 1.4 3.0 Max. 3.6 3.6 3.6 2.7 1.95 1.6 3.6
1. Typical values for VCCO are the average of the min. and max. values.
DC Electrical Characteristics
Over Recommended Operating Conditions
Symbol IIH
1
Parameter Input High Leakage Current I/O Weak Pull-up Resistor Current Bus Hold Low Sustaining Current Bus Hold High Sustaining Current Bus Hold Low Overdrive Current Bus Hold High Overdrive Current Bus Hold Trip Points I/O Capacitance3 Clock Capacitance3 Global Input Capacitance3
Condition 0 VIN < VCCO VCCO < VIN 5.5V 0 VIN 0.7VCCO VIN = VIL (MAX) VIN = 0.7 VCCO 0V VIN VBHT VBHT VIN VCCO -- VCCO = 3.3V, 2.5V, 1.8V, 1.5V VCC = 1.8V, VIO = 0 to VIH (MAX) VCCO = 3.3V, 2.5V, 1.8V, 1.5V VCC = 1.8V, VIO = 0 to VIH (MAX) VCCO = 3.3V, 2.5V, 1.8V, 1.5V VCC = 1.8V, VIO = 0 to VIH (MAX)
Min. -- -- -20 30 30 -20 -- -- VCCO * 0.35 -- -- -- -- -- --
Typ. 0.5 -- -- -- -- -- -- -- -- 8 6 6
Max. 1 10 -150 150 -- -- 150 -150 VCCO * 0.65 -- -- -- -- -- --
Units A A A A A A A A V pf pf pf
IIL, IIH1, 2 Input Leakage Current IPU IPD IBHLS IBHHS IBHLO IBHHO VBHT C1 C2 C3
I/O Weak Pull-down Resistor Current VIL (MAX) VIN VIH (MAX)
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tristated. It is not measured with the output driver active. Bus maintenance circuits are disabled. 2. IIH excursions of up to 1.5A maximum per pin above the spec limit may be observed for certain voltage conditions on no more than 10% of the device's I/O pins. 3. Measured TA = 25C, f = 1.0MHz.
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
Supply Current
Symbol ispMACH 4032ZE Vcc = 1.8V, TA = 25C ICC
1, 2, 3, 5, 6
Parameter
Condition
Min. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Typ. 50 58 60 10 13 15 80 89 92 11 15 18 168 190 195 12 16 19 341 361 372 13 32 43
Max. Units -- -- -- -- 25 40 -- -- -- -- 30 50 -- -- -- -- 40 60 -- -- -- -- 65 100 A A A A A A A A A A A A A A A A A A A A A A A A
Operating Power Supply Current
Vcc = 1.9V, TA = 0 to 70C Vcc = 1.9V, TA = -40 to 85C Vcc = 1.8V, TA = 25C
ICC4, 5, 6
Standby Power Supply Current
Vcc = 1.9V, TA = 0 to 70C Vcc = 1.9V, TA = -40 to 85C
ispMACH 4064ZE Vcc = 1.8V, TA = 25C ICC
1, 2, 3, 5, 6
Operating Power Supply Current
Vcc = 1.9V, TA = 0 to 70C Vcc = 1.9V, TA = -40 to 85C Vcc = 1.8V, TA = 25C
ICC4, 5, 6
Standby Power Supply Current
Vcc = 1.9V, TA = 0 to 70C Vcc = 1.9V, TA = -40 to 85C
ispMACH 4128ZE Vcc = 1.8V, TA = 25C ICC1, 2, 3, 5, 6 Operating Power Supply Current Vcc = 1.9V, TA = 0 to 70C Vcc = 1.9V, TA = -40 to 85C Vcc = 1.8V, TA = 25C ICC4, 5, 6 Standby Power Supply Current Vcc = 1.9V, TA = 0 to 70C Vcc = 1.9V, TA = -40 to 85C ispMACH 4256ZE Vcc = 1.8V, TA = 25C ICC
1, 2, 3, 5, 6
Operating Power Supply Current
Vcc = 1.9V, TA = 0 to 70C Vcc = 1.9V, TA = -40 to 85C Vcc = 1.8V, TA = 25C
ICC4, 5, 6
1. 2. 3. 4. 5. 6.
Standby Power Supply Current
Vcc = 1.9V, TA = 0 to 70C Vcc = 1.9V, TA = -40 to 85C
Frequency = 1.0 MHz. Device configured with 16-bit counters. ICC varies with specific device configuration and operating frequency. VCCO = 3.6V, VIN = 0V or VCCO, bus maintenance turned off. VIN above VCCO will add transient current above the specified standby ICC. Includes VCCO current without output loading. This operating supply current is with the internal oscillator disabled. Enabling the internal oscillator adds approximately 15A typical current plus additional current from any logic it drives.
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
I/O DC Electrical Characteristics
Over Recommended Operating Conditions
VIL Standard LVTTL LVCMOS 3.3 LVCMOS 2.5 LVCMOS 1.8 LVCMOS 1.52 PCI 3.3 Min (V) -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Max (V) 0.80 0.80 0.70 0.35 * VCC 0.35 * VCC VIH Min (V) 2.0 2.0 1.70 0.65 * VCC 0.65 * VCC Max (V) 5.5 5.5 3.6 3.6 3.6 5.5 VOL Max (V) 0.40 0.20 0.40 0.20 0.40 0.20 0.40 0.20 0.40 0.20 0.1 VCCO VOH Min (V) VCCO - 0.40 VCCO - 0.20 VCCO - 0.40 VCCO - 0.20 VCCO - 0.40 VCCO - 0.20 VCCO - 0.45 VCCO - 0.20 VCCO - 0.45 VCCO - 0.20 0.9 VCCO IOL1 (mA) 8.0 0.1 8.0 0.1 8.0 0.1 2.0 0.1 2.0 0.1 1.5 IOH1 (mA) -4.0 -0.1 -4.0 -0.1 -4.0 -0.1 -2.0 -0.1 -2.0 -0.1 -0.5
0.3 * 3.3 * (VCC / 1.8) 0.5 * 3.3 * (VCC / 1.8)
1. The average DC current drawn by I/Os between adjacent bank GND connections, or between the last GND in an I/O bank and the end of the I/O bank, as shown in the logic signals connection table, shall not exceed n*8mA. Where n is the number of I/Os between bank GND connections or between the last GND in a bank and the end of a bank. 2. For 1.5V inputs, there may be an additional DC current drawn from VCC, if the ispMACH 4000ZE VCC and the VCC of the driving device (VCCd-d; that determines steady state VIH) are in the extreme range of their specifications. Typically, DC current drawn from VCC will be 2A per input.
60 Typical I/O Output Current (mA) 50 40 30 20 10 0 0 0.5
1.8V VCCO
IOL IOH
1.0
1.5
2.0
VO Output Voltage (V)
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
ispMACH 4000ZE External Switching Characteristics
Over Recommended Operating Conditions
LC4032ZE -4 Parameter tPD tS tST tSIR tSIRZ tH tHT tHIR tHIRZ tCO tR tRW tPTOE/DIS tGPTOE/DIS tGOE/DIS tCW tGW tWIR Description1, 2 20-PT combinatorial propagation delay GLB register setup time before clock GLB register setup time before clock with T-type register GLB register setup time before clock, input register path GLB register setup time before clock with zero hold GLB register hold time after clock GLB register hold time after clock with T-type register GLB register hold time after clock, input register path GLB register hold time after clock, input register path with zero hold GLB register clock-to-output delay External reset pin to output delay External reset pulse duration Input to output local product term output enable/disable Input to output global product term output enable/disable Global OE input to output enable/disable Global clock width, high or low Global gate width low (for low transparent) or high (for high transparent) Input register clock width, high or low clock frequency with external feedback, [1 / (tS + tCO)] Min. -- 2.2 2.4 1.0 2.0 0.0 0.0 1.0 0.0 -- -- 1.5 -- -- -- 1.0 1.0 1.0 260 192 Max. 4.4 -- -- -- -- -- -- -- -- 3.0 5.0 -- 7.0 6.5 4.5 -- -- -- -- -- Min. -- 2.5 2.7 1.1 2.1 0.0 0.0 1.0 0.0 -- -- 1.7 -- -- -- 1.5 1.5 1.5 241 175 LC4064ZE -4 Max. 4.7 -- -- -- -- -- -- -- -- 3.2 6.0 -- 8.0 7.0 4.5 -- -- -- -- -- Min. -- 2.9 3.1 1.3 2.9 0.0 0.0 1.3 0.0 -- -- 2.0 -- -- -- 1.8 1.8 1.8 200 149 -5 Max. 5.8 -- -- -- -- -- -- -- -- 3.8 7.5 -- 8.2 10.0 5.5 -- -- -- -- -- Min. -- 4.5 4.7 1.4 4.0 0.0 0.0 1.3 0.0 -- -- 4.0 -- -- -- 3.3 3.3 3.3 172 111 All Devices -7 Max. 7.5 -- -- -- -- -- -- -- -- 4.5 9.0 -- 9.0 10.5 7.0 -- -- -- -- -- Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz
fMAX (Int.)3 Clock frequency with internal feedback fMAX (Ext.)
1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards. 2. Measured using standard switching GRP loading of 1 and 1 output switching. 3. Standard 16-bit counter using GRP feedback. Timing v.0.8
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
Timing Model
The task of determining the timing through the ispMACH 4000ZE family, like any CPLD, is relatively simple. The timing model provided in Figure 16 shows the specific delay paths. Once the implementation of a given function is determined either conceptually or from the software report file, the delay path of the function can easily be determined from the timing model. The Lattice design tools report the timing delays based on the same timing model for a particular design. Note that the internal timing parameters are given for reference only, and are not tested. The external timing parameters are tested and guaranteed for every device. For more information on the timing model and usage, please refer to technical note TN1168, ispMACH 4000ZE Timing Model Design and Usage Guidelines. Figure 16. ispMACH 4000ZE Timing Model
Oscillator/ Timer Delays tOSCDIS tOSCEN tOSCOD From Feedback Routing/GLB Delays tPDi IN tIN tIOI tPGRT tGCLK_IN tIOI tPGRT tBIE tROUTE tBLA tINREG tINDIO tMCELL tEXP
DATA
Q
Feedback
tFBK tBUF tIOO tEN tDIS In/Out Delays
Feedback
tORP
Out
SCLK
tPTCLK tBCLK tPTSR tBSR
C.E. S/R MC Reg.
Register/Latch Delays
OE
tGOE tIOI tPGRT In/Out Delays
Control Delays
tGPTOE tPTOE
Note: Italicized items are optional delay adders.
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
ispMACH 4000ZE Internal Timing Parameters
Over Recommended Operating Conditions
LC4032ZE -4 Parameter In/Out Delays tIN tGCLK_IN tGOE tBUF tEN tDIS tPGSU tPGH tPGPW tPGRT Routing Delays tROUTE tPDi tMCELL tINREG tFBK tORP tS tS_PT tH tST tST_PT tHT tSIR tSIR_PT tHIR tHIR_PT tCOi tCES tCEH tSL tSL_PT tHL tGOi tPDLi tSRi Delay through GRP Macrocell Propagation Delay Macrocell Delay Input Buffer to Macrocell Register Delay Internal Feedback Delay Output Routing Pool Delay D-Register Setup Time (Global Clock) D-Register Setup Time (Product Term Clock) D-Register Hold Time T-Register Setup Time (Global Clock) T-register Setup Time (Product Term Clock) T-Resister Hold Time D-Input Register Setup Time (Global Clock) D-Input Register Setup Time (Product Term Clock) D-Input Register Hold Time (Global Clock) D-Input Register Hold Time (Product Term Clock) Register Clock to Output/Feedback MUX Time Clock Enable Setup Time Clock Enable Hold Time Latch Setup Time (Global Clock) Latch Setup Time (Product Term Clock) Latch Hold Time Latch Gate to Output/Feedback MUX Time Propagation Delay through Transparent Latch to Output/ Feedback MUX Asynchronous Reset or Set to Output/Feedback MUX Delay -- -- -- -- -- -- 0.70 1.25 1.50 0.90 1.45 1.50 0.85 1.45 1.15 0.90 -- 1.00 0.00 0.70 1.45 1.40 -- -- -- 1.60 0.25 0.65 0.90 0.55 0.30 -- -- -- -- -- -- -- -- -- -- 0.35 -- -- -- -- -- 0.40 0.30 0.30 -- -- -- -- -- -- 0.85 1.85 1.65 1.05 1.65 1.65 0.80 1.45 1.30 1.10 -- 2.00 0.00 0.95 1.85 1.80 -- -- -- 1.70 0.25 0.65 1.00 0.55 0.30 -- -- -- -- -- -- -- -- -- -- 0.40 -- -- -- -- -- 0.35 0.25 0.30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Input Buffer Delay Global Clock Input Buffer Delay Global OE Pin Delay Delay through Output Buffer Output Enable Time Output Disable Time Input Power Guard Setup Time Input Power Guard Hold Time Input Power Guard BIE Minimum Pulse Width Input Power Guard Recovery Time Following BIE Dissertation -- -- -- -- -- -- -- -- -- -- 0.85 1.60 2.25 0.75 2.25 1.35 3.30 0.00 5.00 5.00 -- -- -- -- -- -- -- -- -- -- 0.90 1.60 2.25 0.90 2.25 1.35 3.55 0.00 5.00 5.00 ns ns ns ns ns ns ns ns ns ns Description Min. Max. Min. LC4064ZE -4 Max. Units
Register/Latch Delays
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
ispMACH 4000ZE Internal Timing Parameters (Cont.)
Over Recommended Operating Conditions
LC4032ZE -4 Parameter tSRR Control Delays tBCLK tPTCLK tBSR tPTSR tBIE tPTOE tGPTOE tOSCSU tOSCH tOSCEN tOSCOD tOSCNOM tOSCvar tTMRCO20 tTMRCO10 tTMRCO7 tTMRRSTO tTMRRR tTMRRSTPW tINDIO tEXP tBLA LVTTL_in LVCMOS15_in LVCMOS18_in LVCMOS25_in LVCMOS33_in PCI_in GLB PT Clock Delay Macrocell PT Clock Delay Block PT Set/Reset Delay Macrocell PT Set/Reset Delay Power Guard Block Input Enable Delay Macrocell PT OE Delay Global PT OE Delay Oscillator DYNOSCDIS Setup Time Oscillator DYNOSCDIS Hold Time Oscillator OSCOUT Enable Time (To Stable) Oscillator Output Delay Oscillator OSCOUT Nominal Frequency Oscillator Variation of Nominal Frequency Oscillator TIMEROUT Clock (Negative Edge) to Out (20-Bit Divider) Oscillator TIMEROUT Clock (Negative Edge) to Out (10-Bit Divider) Oscillator TIMEROUT Clock (Negative Edge) to Out (7-Bit Divider) Oscillator TIMEROUT Reset to Out (Going Low) Oscillator TIMEROUT Asynchronous Reset Recovery Delay Oscillator TIMEROUT Reset Minimum Pulse Width Base Parameter tINREG tMCELL tROUTE tIN, tGCLK_IN, tGOE tIN, tGCLK_IN, tGOE tIN, tGCLK_IN, tGOE tIN, tGCLK_IN, tGOE tIN, tGCLK_IN, tGOE tIN, tGCLK_IN, tGOE -- -- -- -- -- -- -- -- -- 1.00 0.40 0.04 0.60 0.20 0.00 0.80 0.80 0.80 -- -- -- -- -- -- -- -- -- 1.00 0.40 0.05 0.60 0.20 0.00 0.80 0.80 0.80 ns ns ns ns ns ns ns ns ns Input Register Delay Product Term Expander Delay Additional Block Loading Adders Using LVTTL standard Using LVCMOS 1.5 Standard Using LVCMOS 1.8 Standard Using LVCMOS 2.5 Standard with Hysteresis Using LVCMOS 3.3 Standard with Hysteresis Using PCI Compatible Input with Hysteresis Output Configured as TTL Buffer Output Configured as 1.5V Buffer -- -- -- -- -- -- 3.00 -- -- -- -- -- -- -- 5.00 5.00 -- -- 1.20 1.40 1.10 1.20 1.60 2.30 1.80 -- -- 5.00 4.00 5.00 30 12.50 7.50 6.00 5.00 4.00 -- -- -- -- -- -- -- 3.00 -- -- -- -- -- -- -- 5.00 5.00 -- -- 1.30 1.50 1.85 1.90 1.70 3.15 2.15 -- -- 5.00 4.00 5.00 30 12.50 7.50 6.00 5.00 4.00 -- ns ns ns ns ns ns ns ns ns ns ns MHz % ns ns ns ns ns ns Description Asynchronous Reset or Set Recovery Delay Min. -- Max. 2.00 Min. -- LC4064ZE -4 Max. 1.70 Units ns
Internal Oscillator
Optional Delay Adjusters
tIOI Input Buffer Delays
tIOO Output Buffer Delays LVTTL_out LVCMOS15_out tEN, tDIS, tBUF tEN, tDIS, tBUF -- -- 0.20 0.20 -- -- 0.20 0.20 ns ns
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
ispMACH 4000ZE Internal Timing Parameters (Cont.)
Over Recommended Operating Conditions
LC4032ZE -4 Parameter LVCMOS18_out LVCMOS25_out LVCMOS33_out PCI_out Slow Slew Description Output Configured as 1.8V Buffer Output Configured as 2.5V Buffer Output Configured as 3.3V Buffer tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF Min. -- -- -- -- -- Max. 0.00 0.10 0.20 0.20 1.00 Min. -- -- -- -- -- LC4064ZE -4 Max. 0.00 0.10 0.20 0.20 1.00 Units ns ns ns ns ns
Output Configured as PCI Compati- tEN, tDIS, tBUF ble Buffer Output Configured for Slow Slew Rate tEN, tBUF
Note: Internal Timing Parameters are not tested and are for reference only. Refer to the timing model in this data sheet for further details. Timing v.0.8
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
ispMACH 4000ZE Internal Timing Parameters (Cont.)
Over Recommended Operating Conditions
All Devices -5 Parameter In/Out Delays tIN tGCLK_IN tGOE tBUF tEN tDIS tPGSU tPGH tPGPW tPGRT Routing Delays tROUTE tPDi tMCELL tINREG tFBK tORP tS tS_PT tH tST tST_PT tHT tSIR tSIR_PT tHIR tHIR_PT tCOi tCES tCEH tSL tSL_PT tHL tGOi tPDLi tSRi Delay through GRP Macrocell Propagation Delay Macrocell Delay Input Buffer to Macrocell Register Delay Internal Feedback Delay Output Routing Pool Delay D-Register Setup Time (Global Clock) D-Register Setup Time (Product Term Clock) D-Register Hold Time T-Register Setup Time (Global Clock) T-register Setup Time (Product Term Clock) T-Resister Hold Time D-Input Register Setup Time (Global Clock) D-Input Register Setup Time (Product Term Clock) D-Input Register Hold Time (Global Clock) D-Input Register Hold Time (Product Term Clock) Register Clock to Output/Feedback MUX Time Clock Enable Setup Time Clock Enable Hold Time Latch Setup Time (Global Clock) Latch Setup Time (Product Term Clock) Latch Hold Time Latch Gate to Output/Feedback MUX Time Propagation Delay through Transparent Latch to Output/ Feedback MUX Asynchronous Reset or Set to Output/Feedback MUX Delay -- -- -- -- -- -- 0.90 2.00 2.00 1.10 2.20 2.00 1.20 1.45 1.40 1.10 -- 2.00 0.00 0.90 2.00 2.00 -- -- -- 2.25 0.45 0.65 1.00 0.75 0.30 -- -- -- -- -- -- -- -- -- -- 0.45 -- -- -- -- -- 0.35 0.25 0.95 -- -- -- -- -- -- 1.25 2.35 3.25 1.45 2.65 3.25 0.65 1.45 2.05 1.20 -- 2.00 0.00 1.55 2.05 1.17 -- -- -- 2.50 0.50 1.00 1.00 0.30 0.30 -- -- -- -- -- -- -- -- -- -- 0.75 -- -- -- -- -- 0.33 0.25 0.28 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Input Buffer Delay Global Clock Input Buffer Delay Global OE Pin Delay Delay through Output Buffer Output Enable Time Output Disable Time Input Power Guard Setup Time Input Power Guard Hold Time Input Power Guard BIE Minimum Pulse Width Input Power Guard Recovery Time Following BIE Dissertation -- -- -- -- -- -- -- -- -- -- 1.05 1.95 3.00 1.10 2.50 2.50 4.30 0.00 6.00 5.00 -- -- -- -- -- -- -- -- -- -- 1.90 2.15 4.30 1.30 2.70 2.70 5.60 0.00 8.00 7.00 ns ns ns ns ns ns ns ns ns ns Description Min. Max. Min. -7 Max. Units
Register/Latch Delays
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
ispMACH 4000ZE Internal Timing Parameters (Cont.)
Over Recommended Operating Conditions
All Devices -5 Parameter tSRR Control Delays tBCLK tPTCLK tBSR tPTSR tBIE tPTOE tGPTOE tOSCSU tOSCH tOSCEN tOSCOD tOSCNOM tOSCvar tTMRCO20 tTMRCO10 tTMRCO7 tTMRRSTO tTMRRR tTMRRSTPW tINDIO tEXP tBLA LVTTL_in LVCMOS15_in LVCMOS18_in LVCMOS25_in LVCMOS33_in PCI_in GLB PT Clock Delay Macrocell PT Clock Delay Block PT Set/Reset Delay Macrocell PT Set/Reset Delay Power Guard Block Input Enable Delay Macrocell PT OE Delay Global PT OE Delay Oscillator DYNOSCDIS Setup Time Oscillator DYNOSCDIS Hold Time Oscillator OSCOUT Enable Time (To Stable) Oscillator Output Delay Oscillator OSCOUT Nominal Frequency Oscillator Variation of Nominal Frequency Oscillator TIMEROUT Clock (Negative Edge) to Out (20-Bit Divider) Oscillator TIMEROUT Clock (Negative Edge) to Out (10-Bit Divider) Oscillator TIMEROUT Clock (Negative Edge) to Out (7-Bit Divider) Oscillator TIMEROUT Reset to Out (Going Low) Oscillator TIMEROUT Asynchronous Reset Recovery Delay Oscillator TIMEROUT Reset Minimum Pulse Width Base Parameter tINREG tMCELL tROUTE tIN, tGCLK_IN, tGOE tIN, tGCLK_IN, tGOE tIN, tGCLK_IN, tGOE tIN, tGCLK_IN, tGOE tIN, tGCLK_IN, tGOE tIN, tGCLK_IN, tGOE -- -- -- -- -- -- -- -- -- 1.60 0.45 0.05 0.60 0.20 0.00 0.80 0.80 0.80 -- -- -- -- -- -- -- -- -- 2.60 0.50 0.05 0.60 0.20 0.00 0.80 0.80 0.80 ns ns ns ns ns ns ns ns ns Input Register Delay Product Term Expander Delay Additional Block Loading Adders Using LVTTL standard Using LVCMOS 1.5 standard Using LVCMOS 1.8 standard Using LVCMOS 2.5 standard with Hysteresis Using LVCMOS 3.3 standard with Hysteresis Using PCI compatible input with Hysteresis Output configured as TTL buffer -- -- -- -- -- -- 3.00 -- -- -- -- -- -- -- 5.00 5.00 -- -- 1.45 1.45 1.85 1.85 1.75 2.40 4.20 -- -- 5.00 4.00 5.00 30 12.50 7.50 6.00 5.00 4.00 -- -- -- -- -- -- -- 5.00 -- -- -- -- -- -- -- 5.00 5.00 -- -- 0.95 1.15 1.83 2.72 1.95 1.90 3.40 -- -- 5.00 4.00 5.00 30 14.50 9.50 8.00 7.00 6.00 -- ns ns ns ns ns ns ns ns ns ns ns MHz % ns ns ns ns ns ns Description Asynchronous Reset or Set Recovery Delay Min. -- Max. 1.80 Min. -- -7 Max. 1.67 Units ns
Internal Oscillator
Optional Delay Adjusters
tIOI Input Buffer Delays
tIOO Output Buffer Delays LVTTL_out tEN, tDIS, tBUF -- 0.20 -- 0.20 ns
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
ispMACH 4000ZE Internal Timing Parameters (Cont.)
Over Recommended Operating Conditions
All Devices -5 Parameter LVCMOS15_out LVCMOS18_out LVCMOS25_out LVCMOS33_out PCI_out Slow Slew Description Output configured as 1.5V buffer Output configured as 1.8V buffer Output configured as 2.5V buffer Output configured as 3.3V buffer tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF Min. -- -- -- -- -- -- Max. 0.20 0.00 0.10 0.20 0.20 1.00 Min. -- -- -- -- -- -- -7 Max. 0.20 0.00 0.10 0.20 0.20 1.00 Units ns ns ns ns ns ns
Output configured as PCI compati- tEN, tDIS, tBUF ble buffer Output configured for slow slew rate tEN, tBUF
Note: Internal Timing Parameters are not tested and are for reference only. Refer to the timing model in this data sheet for further details. Timing v.0.8
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
Boundary Scan Waveforms and Timing Specifications
Symbol tBTCP tBTCH tBTCL tBTSU tBTH tBRF tBTCO tBTOZ tBTVO tBTCPSU tBTCPH tBTUCO tBTUOZ tBTUOV TCK [BSCAN test] clock cycle TCK [BSCAN test] pulse width high TCK [BSCAN test] pulse width low TCK [BSCAN test] setup time TCK [BSCAN test] hold time TCK [BSCAN test] rise and fall time TAP controller falling edge of clock to valid output TAP controller falling edge of clock to data output disable TAP controller falling edge of clock to data output enable BSCAN test Capture register setup time BSCAN test Capture register hold time BSCAN test Update reg, falling edge of clock to valid output BSCAN test Update reg, falling edge of clock to output disable BSCAN test Update reg, falling edge of clock to output enable Parameter Min. 40 20 20 8 10 50 -- -- -- 8 10 -- -- -- Max. -- -- -- -- -- -- 10 10 10 -- -- 25 25 25 Units ns ns ns ns ns mV/ns ns ns ns ns ns ns ns ns
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
Power Consumption
ispMACH 4000ZE Typical ICC vs. Frequency
70
60
4256ZE
50
Icc (mA)
40
4128ZE
30
20
4064ZE 4032ZE
10
0 0 50 100 150 200 250 300 Frequency (MHz)
Power Estimation Coefficients1
Device ispMACH 4032ZE ispMACH 4064ZE ispMACH 4128ZE ispMACH 4256ZE A 0.010 0.011 0.012 0.013 B 0.009 0.009 0.009 0.009
1. For further information about the use of these coefficients, refer to Technical Note TN1175, Power Estimation in ispMACH 4000ZE Devices.
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
Switching Test Conditions
Figure 17 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Table 13. Figure 17. Output Test Load, LVTTL and LVCMOS Standards VCCO R1 DUT R2 CL Test Point
0213A/ispm4k
Table 13. Test Fixture Required Components
Test Condition R1 R2 CL1 Timing Ref. LVCMOS 3.3 = 1.5V LVCMOS 2.5 = LVCMOS I/O, (L -> H, H -> L) 106 106 35pF LVCMOS 1.8 = VCCO 2 VCCO 2 VCCO 2 VCCO LVCMOS 3.3 = 3.0V LVCMOS 2.5 = 2.3V
LVCMOS 1.8 = 1.65V
LVCMOS 1.5 = LVCMOS I/O (Z -> H) LVCMOS I/O (Z -> L) LVCMOS I/O (H -> Z) LVCMOS I/O (L -> Z)
1. CL includes test fixtures and probe capacitance.
LVCMOS 1.5 = 1.4V 3.0V 3.0V 3.0V 3.0V
106 106
106 106
35pF 35pF 5pF 5pF
1.5V 1.5V VOH - 0.3 VOL + 0.3
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
Signal Descriptions
Signal Names TMS TCK TDI TDO GOE0/IO, GOE1/IO GND NC VCC CLK0/I, CLK1/I, CLK2/I, CLK3/I VCCO0, VCCO1 Description Input - This pin is the IEEE 1149.1 Test Mode Select input, which is used to control the state machine. Input - This pin is the IEEE 1149.1 Test Clock input pin, used to clock through the state machine. Input - This pin is the IEEE 1149.1 Test Data In pin, used to load data. Output - This pin is the IEEE 1149.1 Test Data Out pin used to shift data out. These pins are configured to be either Global Output Enable Input or as general I/O pins. Ground Not Connected The power supply pins for logic core and JTAG port. These pins are configured to be either CLK input or as an input. The power supply pins for each I/O bank. Input/Output1 - These are the general purpose I/O used by the logic array. y is GLB reference (alpha) and z is macrocell reference (numeric). z: 0-15. ispMACH 4032ZE yzz ispMACH 4064ZE ispMACH 4128ZE ispMACH 4256ZE
1. In some packages, certain I/Os are only available for use as inputs. See the signal connections table for details.
y: A-B y: A-D y: A-H y: A-P
ORP Reference Table
4032ZE Number of I/Os Number of GLBs Number of I/Os per GLB Reference ORP Table (I/Os per GLB) 32 2 16 32 4 8 4064ZE 48 4 Mixture of 9, 10, 14, 15 9, 10, 14, 15 64 4 16 64 8 8 4128ZE 96 8 12 64 16 4 4256ZE 96 16 6 108 16 Mixture of 6, 7, 8 6, 7, 8
16
8
16
8
12
4
6
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
ispMACH 4000ZE Power Supply and NC Connections1
Signal VCC VCCO0 VCCO (Bank 0) VCCO1 VCCO (Bank 1) GND GND (Bank 0) GND (Bank 1) NC 12, 36 6 30 13, 37 5 29 -- 48 TQFP2 E4, D5 4032ZE: E3 4064ZE: E3, F4 4032ZE: D6 4064ZE: D6, C6 D4, E5 D4, E5 D4, E5 -- 64 csBGA3, 4 100 TQFP2 25, 40, 75, 90 13, 33, 95 45, 63, 83 1, 26, 51, 76 7, 18, 32, 96 46, 57, 68, 82 --
1. All grounds must be electrically connected at the board level. However, for the purposes of I/O current loading, grounds are associated with the bank shown. 2. Pin orientation follows the conventional order from pin 1 marking of the top side view and counter-clockwise. 3. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order ascending horizontally. 4. All bonded grounds are connected to the following two balls, D4 and E5.
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
ispMACH 4000ZE Power Supply and NC Connections1 (Cont.)
Signal VCC H5, H8, E8, E5 VCCO0 E4, F4, G4, J5, D5 VCCO (Bank 0) J8, H9, G9, F9, D8 VCCO1 VCCO (Bank 1) GND GND (Bank 0) GND (Bank 1) NC F6, G6, G7, F7 G5, H4, H6, E6, F5 H7, J9, G8, F8, E7 144 csBGA3 36, 57, 108, 129 3, 19, 34, 47, 136 64, 75, 91, 106, 119 1, 37, 73, 109 10, 184, 27, 46, 127, 137 55, 65, 82, 904, 99, 118 144 TQFP2
4064ZE: E4, B2, B1, D2, D3, E1, H1, H3, H2, L1, G4, 4128ZE: 17, 20, 38, 45, 72, 89, 92, 110, 117, 144 M1, K3, M2, M4, L5, H7, L8, M8, L10, K9, M11, H9, 4256ZE: 18, 90 L12, L11, J12, J11, H10, D10, F10, D12, B12, F9, A12, C10, B10, A9, B8, E6, B5, A5, C4, B3, A2 4128ZE: D2, D3, H2, M1, K3, M11, J12, J11, D12, A12, C10, A2
1. All grounds must be electrically connected at the board level. However, for the purposes of I/O current loading, grounds are associated with the bank shown. 2. Pin orientation follows the conventional order from pin 1 marking of the top side view and counter-clockwise. 3. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order ascending horizontally. 4. For the LC4256ZE, pins 18 and 90 are no connects.
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
ispMACH 4032ZE and 4064ZE Logic Signal Connections: 48 TQFP
ispMACH 4032ZE Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GLB/MC/Pad TDI A5 A6 A7 GND (Bank 0) VCCO (Bank 0) A8 A9 A10 A11 TCK VCC GND A12 A13 A14 A15 CLK1/I CLK2/I B0 B1 B2 B3 B4 TMS B5 B6 B7 GND (Bank 1) VCCO (Bank 1) B8 B9 B10 B11 TDO VCC GND B12 B13 B14 B15/GOE1 CLK3/I ispMACH 4064ZE GLB/MC/Pad TDI A8 A10 A11 GND (Bank 0) VCCO (Bank 0) B15 B12 B10 B8 TCK VCC GND B6 B4 B2 B0 CLK1/I CLK2/I C0 C1 C2 C4 C6 TMS C8 C10 C11 GND (Bank 1) VCCO (Bank 1) D15 D12 D10 D8 TDO VCC GND D6 D4 D2 D0/GOE1 CLK3/I
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
ispMACH 4032ZE and 4064ZE Logic Signal Connections: 48 TQFP (Cont.)
ispMACH 4032ZE Pin Number 43 44 45 46 47 48 Bank Number 0 0 0 0 0 0 GLB/MC/Pad CLK0/I A0/GOE0 A1 A2 A3 A4 ispMACH 4064ZE GLB/MC/Pad CLK0/I A0/GOE0 A1 A2 A4 A6
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
ispMACH 4032ZE and 4064ZE Logic Signal Connections: 64 csBGA
ispMACH 4032ZE Ball Number B2 B1 C2 C1 GND* C3 E3 D1 D2 E1 D3 F1 E2 G1 F2 H1 E4 GND* G2 H2 H3 GND* F4 G3 F3 H4 G4 H5 F5 G5 G6 H6 F6 H7 H8 G7 F7 G8 GND* F8 D6 E8 Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GLB/MC/Pad TDI A5 A6 A7 GND (Bank 0) NC VCCO (Bank 0) A8 NC A9 A10 A11 NC NC NC TCK VCC GND A12 NC A13 NC NC A14 NC A15 CLK1/I CLK2/I B0 B1 B2 B3 B4 NC TMS B5 B6 B7 GND (Bank 0) NC VCCO (Bank 1) B8 ispMACH 4064ZE GLB/MC/Pad TDI A8 A10 A11 GND (Bank 0) A12 VCCO (Bank 0) B15 B14 B13 B12 B11 B10 B9 B8 TCK VCC GND B6 B5 B4 GND (Bank 0) VCCO (Bank 0) B3 B2 B0 CLK1/I CLK2/I C0 C1 C2 C4 C5 C6 TMS C8 C10 C11 GND (Bank 1) C12 VCCO (Bank 1) D15
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
ispMACH 4032ZE and 4064ZE Logic Signal Connections: 64 csBGA (Cont.)
ispMACH 4032ZE Ball Number E7 E6 D7 D8 C5 C7 C8 B8 D5 GND* A8 A7 B7 A6 GND* C6 B6 A5 B5 A4 C4 B4 B3 A3 A2 A1 Bank Number 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 GLB/MC/Pad NC B9 B10 NC NC B11 NC TDO VCC GND B12 NC NC B13 NC NC B14 NC B15/GOE1 CLK3/I CLK0/I A0/GOE0 A1 A2 A3 A4 ispMACH 4064ZE GLB/MC/Pad D14 D13 D12 D11 D10 D9 D8 TDO VCC GND D7 D6 D5 D4 GND (Bank 1) VCCO (Bank 1) D3 D2 D0/GOE1 CLK3/I CLK0/I A0/GOE0 A1 A2 A4 A6
* All bonded grounds are connected to the following two balls, D4 and E5.
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
ispMACH 4064ZE, 4128ZE and 4256ZE Logic Signal Connections: 100 TQFP
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12* 13 14 15 16 17 18 19 20 21 22 23* 24 25 26 27* 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 LC4064ZE GLB/MC/Pad GND TDI A8 A9 A10 A11 GND (Bank 0) A12 A13 A14 A15 I VCCO (Bank 0) B15 B14 B13 B12 GND (Bank 0) B11 B10 B9 B8 I TCK VCC GND I B7 B6 B5 B4 GND (Bank 0) VCCO (Bank 0) B3 B2 B1 B0 CLK1/I CLK2/I VCC C0 LC4128ZE GLB/MC/Pad GND TDI B0 B2 B4 B6 GND (Bank 0) B8 B10 B12 B13 I VCCO (Bank 0) C14 C12 C10 C8 GND (Bank 0) C6 C5 C4 C2 I TCK VCC GND I D13 D12 D10 D8 GND (Bank 0) VCCO (Bank 0) D6 D4 D2 D0 CLK1/I CLK2/I VCC E0 LC4256ZE GLB/MC/Pad GND TDI C12 C10 C6 C2 GND (Bank 0) D12 D10 D6 D4 I VCCO (Bank 0) E4 E6 E10 E12 GND (Bank 0) F2 F6 F10 F12 I TCK VCC GND I G12 G10 G6 G2 GND (Bank 0) VCCO (Bank 0) H12 H10 H6 H2 CLK1/I CLK2/I VCC I2
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
ispMACH 4064ZE, 4128ZE and 4256ZE Logic Signal Connections: 100 TQFP (Cont.)
Pin Number 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62* 63 64 65 66 67 68 69 70 71 72 73* 74 75 76 77* 78 79 80 81 82 Bank Number 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LC4064ZE GLB/MC/Pad C1 C2 C3 VCCO (Bank 1) GND (Bank 1) C4 C5 C6 C7 GND TMS C8 C9 C10 C11 GND (Bank 1) C12 C13 C14 C15 I VCCO (Bank 1) D15 D14 D13 D12 GND (Bank 1) D11 D10 D9 D8 I TDO VCC GND I D7 D6 D5 D4 GND (Bank 1) LC4128ZE GLB/MC/Pad E2 E4 E6 VCCO (Bank 1) GND (Bank 1) E8 E10 E12 E14 GND TMS F0 F2 F4 F6 GND (Bank 1) F8 F10 F12 F13 I VCCO (Bank 1) G14 G12 G10 G8 GND (Bank 1) G6 G5 G4 G2 I TDO VCC GND I H13 H12 H10 H8 GND (Bank 1) LC4256ZE GLB/MC/Pad I6 I10 I12 VCCO (Bank 1) GND (Bank 1) J2 J6 J10 J12 GND TMS K12 K10 K6 K2 GND (Bank 1) L12 L10 L6 L4 I VCCO (Bank 1) M4 M6 M10 M12 GND (Bank 1) N2 N6 N10 N12 I TDO VCC GND I O12 O10 O6 O2 GND (Bank 1)
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
ispMACH 4064ZE, 4128ZE and 4256ZE Logic Signal Connections: 100 TQFP (Cont.)
Pin Number 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
* This pin is input only.
Bank Number 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
LC4064ZE GLB/MC/Pad VCCO (Bank 1) D3 D2 D1 D0/GOE1 CLK3/I CLK0/I VCC A0/GOE0 A1 A2 A3 VCCO (Bank 0) GND (Bank 0) A4 A5 A6 A7
LC4128ZE GLB/MC/Pad VCCO (Bank 1) H6 H4 H2 H0/GOE1 CLK3/I CLK0/I VCC A0/GOE0 A2 A4 A6 VCCO (Bank 0) GND (Bank 0) A8 A10 A12 A14
LC4256ZE GLB/MC/Pad VCCO (Bank 1) P12 P10 P6 P2/GOE1 CLK3/I CLK0/I VCC A2/GOE0 A6 A10 A12 VCCO (Bank 0) GND (Bank 0) B2 B6 B10 B12
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
ispMACH 4064ZE, 4128ZE and 4256ZE Logic Signal Connections: 144 csBGA
Ball Number F6 A1 E4 B2 B1 C3 C2 C1 D1 G5 D2 D3 E1 E2 F2 D4 F1 F3* F4 G1 E3 G2 G3 H1 H3 H2 H4 J1 J3 J2 K1 K2* L1 G4 L2 H5 G6 M1 K3 M2 L3* Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LC4064ZE GLB/MC/Pad GND TDI NC Ball NC Ball NC Ball A8 A9 A10 A11 GND (Bank 0) NC Ball NC Ball NC Ball A12 A13 A14 A15 I VCCO (Bank 0) B15 B14 B13 B12 NC Ball NC Ball NC Ball GND (Bank 0) B11 B10 B9 B8 I NC Ball NC Ball TCK VCC GND NC Ball NC Ball NC Ball I LC4128ZE GLB/MC/Pad GND TDI VCCO (Bank 0) B0 B1 B2 B4 B5 B6 GND (Bank 0) NC Ball NC Ball B8 B9 B10 B12 B13 B14 VCCO (Bank 0) C14 C13 C12 C10 C9 C8 NC Ball GND (Bank 0) C6 C5 C4 C2 C1 C0 VCCO (Bank 0) TCK VCC GND NC Ball NC Ball D14 D13 LC4256ZE GLB/MC/Pad GND TDI VCCO (Bank 0) C12 C10 C8 C6 C4 C2 GND (Bank 0) D14 D12 D10 D8 D6 D4 D2 D0 VCCO (Bank 0) E0 E2 E4 E6 E8 E10 E12 GND (Bank 0) F2 F4 F6 F8 F10 F12 VCCO (Bank 0) TCK VCC GND G14 G12 G10 G8
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
ispMACH 4064ZE, 4128ZE and 4256ZE Logic Signal Connections: 144 csBGA (Cont.)
Ball Number J4 K4 M3 L4 H6 J5 M4 L5 K5 J6 M5 K6 L6 H7 M6 H8 K7 M7 L7 J7 L8 M8 J8 J9 M9 L9 K8 M10 L10 K9 M11 G7 M12 H9 L12 L11 K10 K12 J10 K11 G8 Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LC4064ZE GLB/MC/Pad B7 B6 B5 B4 GND (Bank 0) VCCO (Bank 0) NC Ball NC Ball B3 B2 B1 B0 CLK1/I NC Ball CLK2/I VCC C0 C1 C2 C3 NC Ball NC Ball VCCO (Bank 1) GND (Bank 1) C4 C5 C6 C7 NC Ball NC Ball NC Ball GND TMS NC Ball NC Ball NC Ball C8 C9 C10 C11 GND (Bank 1) LC4128ZE GLB/MC/Pad D12 D10 D9 D8 GND (Bank 0) VCCO (Bank 0) D6 D5 D4 D2 D1 D0 CLK1/I GND (Bank 1) CLK2/I VCC E0 E1 E2 E4 E5 E6 VCCO (Bank 1) GND (Bank 1) E8 E9 E10 E12 E13 E14 NC Ball GND TMS VCCO (Bank 1) F0 F1 F2 F4 F5 F6 GND (Bank 1) LC4256ZE GLB/MC/Pad G6 G4 G2 G0 GND (Bank 0) VCCO (Bank 0) H12 H10 H8 H6 H4 H2 CLK1/I GND (Bank 1) CLK2/I VCC I2 I4 I6 I8 I10 I12 VCCO (Bank 1) GND (Bank 1) J2 J4 J6 J8 J10 J12 J14 GND TMS VCCO (Bank 1) K12 K10 K8 K6 K4 K2 GND (Bank 1)
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
ispMACH 4064ZE, 4128ZE and 4256ZE Logic Signal Connections: 144 csBGA (Cont.)
Ball Number J12 J11 H10 H12 G11 H11 G12 G10* G9 F12 F11 E11 E12 D10 F10 D12 F8 E10 D11 E9 C12 C11* B12 F9 B11 E8 F7 A12 C10 B10 A11* D9 B9 C9 A10 E7 D8 A9 B8 C8 A8 Bank Number 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LC4064ZE GLB/MC/Pad NC Ball NC Ball NC Ball C12 C13 C14 C15 I VCCO (Bank 1) D15 D14 D13 D12 NC Ball NC Ball NC Ball GND (Bank 1) D11 D10 D9 D8 I NC Ball NC Ball TDO VCC GND NC Ball NC Ball NC Ball I D7 D6 D5 D4 GND (Bank 1) VCCO (Bank 1) NC Ball NC Ball D3 D2 LC4128ZE GLB/MC/Pad NC Ball NC Ball F8 F9 F10 F12 F13 F14 VCCO (Bank 1) G14 G13 G12 G10 G9 G8 NC Ball GND (Bank 1) G6 G5 G4 G2 G1 G0 VCCO (Bank 1) TDO VCC GND NC Ball NC Ball H14 H13 H12 H10 H9 H8 GND (Bank 1) VCCO (Bank 1) H6 H5 H4 H2 LC4256ZE GLB/MC/Pad L14 L12 L10 L8 L6 L4 L2 L0 VCCO (Bank 1) M0 M2 M4 M6 M8 M10 M12 GND (Bank 1) N2 N4 N6 N8 N10 N12 VCCO (Bank 1) TDO VCC GND O14 O12 O10 O8 O6 O4 O2 O0 GND (Bank 1) VCCO (Bank 1) P12 P10 P8 P6
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
ispMACH 4064ZE, 4128ZE and 4256ZE Logic Signal Connections: 144 csBGA (Cont.)
Ball Number D7 B7 C7 E6 A7 E5 D6 B6 A6 C6 B5 A5 D5 F5 A4 B4 C5 A3 C4 B3 A2 Bank Number 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LC4064ZE GLB/MC/Pad D1 D0/GOE1 CLK3/I NC Ball CLK0/I VCC A0/GOE0 A1 A2 A3 NC Ball NC Ball VCCO (Bank 0) GND (Bank 0) A4 A5 A6 A7 NC Ball NC Ball NC Ball LC4128ZE GLB/MC/Pad H1 H0/GOE1 CLK3/I GND (Bank 0) CLK0/I VCC A0/GOE0 A1 A2 A4 A5 A6 VCCO (Bank 0) GND (Bank 0) A8 A9 A10 A12 A13 A14 NC Ball LC4256ZE GLB/MC/Pad P4 P2/GOE1 CLK3/I GND (Bank 0) CLK0/I VCC A2/GOE0 A4 A6 A8 A10 A12 VCCO (Bank 0) GND (Bank 0) B2 B4 B6 B8 B10 B12 B14
* This pin is input only for the LC4064ZE.
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
ispMACH 4128ZE and 4256ZE Logic Signal Connections: 144 TQFP
LC4128ZE Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17* 18 19 20* 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38* 39 40 41 42 Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GLB/MC/Pad GND TDI VCCO (Bank 0) B0 B1 B2 B4 B5 B6 GND (Bank 0) B8 B9 B10 B12 B13 B14 NC GND (Bank 0) VCCO (Bank 0) NC C14 C13 C12 C10 C9 C8 GND (Bank 0) C6 C5 C4 C2 C1 C0 VCCO (Bank 0) TCK VCC GND NC D14 D13 D12 D10 LC4256ZE GLB/MC/Pad GND TDI VCCO (Bank 0) C12 C10 C8 C6 C4 C2 GND (Bank 0) D14 D12 D10 D8 D6 D4 I NC VCCO (Bank 0) I E2 E4 E6 E8 E10 E12 GND (Bank 0) F2 F4 F6 F8 F10 F12 VCCO (Bank 0) TCK VCC GND I G12 G10 G8 G6
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
ispMACH 4128ZE and 4256ZE Logic Signal Connections: 144 TQFP (Cont.)
LC4128ZE Pin Number 43 44 45* 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72* 73 74 75 76 77 78 79 80 81 82 83 84 85 Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GLB/MC/Pad D9 D8 NC GND (Bank 0) VCCO (Bank 0) D6 D5 D4 D2 D1 D0 CLK1/I GND (Bank 1) CLK2/I VCC E0 E1 E2 E4 E5 E6 VCCO (Bank 1) GND (Bank 1) E8 E9 E10 E12 E13 E14 NC GND TMS VCCO (Bank 1) F0 F1 F2 F4 F5 F6 GND (Bank 1) F8 F9 F10 LC4256ZE GLB/MC/Pad G4 G2 I GND (Bank 0) VCCO (Bank 0) H12 H10 H8 H6 H4 H2 CLK1/I GND (Bank 1) CLK2/I VCC I2 I4 I6 I8 I10 I12 VCCO (Bank 1) GND (Bank 1) J2 J4 J6 J8 J10 J12 I GND TMS VCCO (Bank 1) K12 K10 K8 K6 K4 K2 GND (Bank 1) L14 L12 L10
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
ispMACH 4128ZE and 4256ZE Logic Signal Connections: 144 TQFP (Cont.)
LC4128ZE Pin Number 86 87 88 89* 90 91 92* 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110* 111 112 113 114 115 116 117* 118 119 120 121 122 123 124 125 126 127 128 Bank Number 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 GLB/MC/Pad F12 F13 F14 NC GND (Bank 1) VCCO (Bank 1) NC G14 G13 G12 G10 G9 G8 GND (Bank 1) G6 G5 G4 G2 G1 G0 VCCO (Bank 1) TDO VCC GND NC H14 H13 H12 H10 H9 H8 NC GND (Bank 1) VCCO (Bank 1) H6 H5 H4 H2 H1 H0/GOE1 CLK3/I GND (Bank 0) CLK0/I LC4256ZE GLB/MC/Pad L8 L6 L4 I NC VCCO (Bank 1) I M2 M4 M6 M8 M10 M12 GND (Bank 1) N2 N4 N6 N8 N10 N12 VCCO (Bank 1) TDO VCC GND I O12 O10 O8 O6 O4 O2 I GND (Bank 1) VCCO (Bank 1) P12 P10 P8 P6 P4 P2/GOE1 CLK3/I GND (Bank 0) CLK0/I
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
ispMACH 4128ZE and 4256ZE Logic Signal Connections: 144 TQFP (Cont.)
LC4128ZE Pin Number 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144*
* This pin is input only for the LC4256ZE.
LC4256ZE GLB/MC/Pad VCC A2/GOE0 A4 A6 A8 A10 A12 VCCO (Bank 0) GND (Bank 0) B2 B4 B6 B8 B10 B12 I
Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GLB/MC/Pad VCC A0/GOE0 A1 A2 A4 A5 A6 VCCO (Bank 0) GND (Bank 0) A8 A9 A10 A12 A13 A14 NC
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
Part Number Description
LC XXXX XX - XX XX XXX X XX
Device Family Device Number 4032 = 32 Macrocells 4064 = 64 Macrocells 4128 = 128 Macrocells 4256 = 256 Macrocells Power ZE = Zero Power, Enhanced Speed 4 = 4.4ns (4032ZE Only) 4 = 4.7ns (4064ZE Only) 5 = 5.8ns (All Devices) 7 = 7.5ns (All Devices) Production Status Blank = Final production device ES = Engineering samples Operating Temperature Range C = Commercial I = Industrial Pin/Ball Count 48 (1.0 mm thickness) 64 100 144 Package TN = Lead-free TQFP MN = Lead-free csBGA
ispMACH 4000ZE Family Speed Grade Offering
-4 Com ispMACH 4032ZE ispMACH 4064ZE ispMACH 4128ZE ispMACH 4256ZE Com -5 Ind Com -7 Ind
Ordering Information
Note: ispMACH 4000ZE devices are dual marked except for the slowest commercial speed grade. For example, the commercial speed grade LC4128ZE-5TN100C is also marked with the industrial grade -7I. The commercial grade is always one speed grade faster than the associated dual mark industrial grade. The slowest commercial speed grade devices are marked as commercial grade only. The markings appear as follows: Figure 18. Mark Format for 100 TQFP and 144 TQFP Packages
ispMACH
ispMACH
LC4128ZE 5TN100C-7I Datecode Dual Mark
LC4128ZE 7TN100C Datecode Single Mark
Figure 19. Mark Format for 48 TQFP, 64 csBGA and 144 csBGA Packages
ispMACH
ispMACH
LC4032ZE 5MN-7I Datecode Dual Mark
LC4032ZE 7MN Datecode Single Mark
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Lattice Semiconductor Lead-Free Packaging
ispMACH 4000ZE Family Data Sheet
Commercial Devices
Device Part Number LC4032ZE-4TN48C LC4032ZE-5TN48C LC4032ZE LC4032ZE-7TN48C LC4032ZE-4MN64C LC4032ZE-5MN64C LC4032ZE-7MN64C LC4064ZE-4TN48C LC4064ZE-5TN48C LC4064ZE-7TN48C LC4064ZE-4TN100C LC4064ZE-5TN100C LC4046ZE LC4064ZE-7TN100C LC4064ZE-4MN64C LC4064ZE-5MN64C LC4064ZE-7MN64C LC4064ZE-4MN144C LC4064ZE-5MN144C LC4064ZE-7MN144C LC4128ZE-5TN100C LC4128ZE-7TN100C LC4128ZE LC4128ZE-5TN144C LC4128ZE-7TN144C LC4128ZE-5MN144C LC4128ZE-7MN144C LC4256ZE-5TN100C LC4256ZE-7TN100C LC4256ZE LC4256ZE-5TN144C LC4256ZE-7TN144C LC4256ZE-5MN144C LC4256ZE-7MN144C Macrocells 32 32 32 32 32 32 64 64 64 64 64 64 64 64 64 64 64 64 128 128 128 128 128 128 256 256 256 256 256 256 Voltage 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 tPD 4.4 5.8 7.5 4.4 5.8 7.5 4.7 5.8 7.5 4.7 5.8 7.5 4.7 5.8 7.5 4.7 5.8 7.5 5.8 7.5 5.8 7.5 5.8 7.5 5.8 7.5 5.8 7.5 5.8 7.5 Package Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free csBGA Lead-Free csBGA Lead-Free csBGA Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free csBGA Lead-Free csBGA Lead-Free csBGA Lead-Free csBGA Lead-Free csBGA Lead-Free csBGA Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free csBGA Lead-Free csBGA Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free csBGA Lead-Free csBGA Pin/Ball Count 48 48 48 64 64 64 48 48 48 100 100 100 64 64 64 144 144 144 100 100 144 144 144 144 100 100 144 144 144 144 I/O 32 32 32 32 32 32 32 32 32 64 64 64 48 48 48 64 64 64 64 64 96 96 96 96 64 64 96 96 108 108 Grade C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
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Lattice Semiconductor
Industrial
Device Part Number LC4032ZE-5TN48I LC4032ZE LC4032ZE-7TN48I LC4032ZE-5MN64I LC4032ZE-7MN64I LC4064ZE-5TN48I LC4064ZE-7TN48I LC4064ZE-5TN100I LC4064ZE LC4064ZE-7TN100I LC4064ZE-5MN64I LC4064ZE-7MN64I LC4064ZE-5MN144I LC4064ZE-7MN144I LC4128ZE-7TN100I LC4128ZE LC4128ZE-7TN144I LC4128ZE-7MN144I LC4256ZE-7TN100I LC4256ZE LC4256ZE-7TN144I LC4256ZE-7MN144I Macrocells 32 32 32 32 64 64 64 64 64 64 64 64 128 128 128 256 256 256 Voltage 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 tPD 5.8 7.5 5.8 7.5 5.8 7.5 5.8 7.5 5.8 7.5 5.8 7.5 7.5 7.5 7.5 7.5 7.5 7.5
ispMACH 4000ZE Family Data Sheet
Package Lead-Free TQFP Lead-Free TQFP Lead-Free csBGA Lead-Free csBGA Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free csBGA Lead-Free csBGA Lead-Free csBGA Lead-Free csBGA Lead-Free TQFP Lead-Free TQFP Lead-Free csBGA Lead-Free TQFP Lead-Free TQFP Lead-Free csBGA
Pin/Ball Count 48 48 64 64 48 48 100 100 64 64 144 144 100 144 144 100 144 144
I/O 32 32 32 32 32 32 64 64 48 48 64 64 64 96 96 64 96 108
Grade I I I I I I I I I I I I I I I I I I
For Further Information
In addition to this data sheet, the following technical notes may be helpful when designing with the ispMACH 4000ZE family: * TN1168 - ispMACH 4000ZE Timing Model Design and Usage Guidelines * TN1174 - Advanced Features of the ispMACH 4000ZE * TN1175 - Power Estimation and Management for ispMACH 4000ZE Devices
Technical Support Assistance
Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: techsupport@latticesemi.com Internet: www.latticesemi.com
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
Revision History
Date April 2008 July 2008 Version 01.0 01.1 Initial release. Updated Features bullets. Updated typical Hysteresis voltage. Updated Power Guard for Dedicated Inputs section. Updated DC Electrical Characteristics table. Updated Supply Current table. Updated I/O DC Electrical Characteristics table and note 2. Updated ispMACH 4000ZE Timing Model. Added new parameters for the Internal Oscillator. Updated ORP Reference table. Updated Power Supply and NC Connections table. Updated 100 TQFP Logic Signal Connections table with LC4128ZE and 4256ZE. Updated 144 csBGA Logic Signal Connections table with LC4128ZE and 4256ZE. Added 144 TQFP Logic Signal Connections table. August 2008 01.2 Data sheet status changed from advance to final. Updated Supply Current table. Updated External Switching Characteristics. Updated Internal Timing Parameters. Updated Power Consumption graph and Power Estimation Coefficients table. Updated Ordering Information mark format example. Change Summary
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